Sunday, August 27, 2006
OpenSPARC T1 uArch Spec Released
Direct link: http://opensparc-t1.sunsource.net/specs/OpenSPARCT1_Micro_Arch.pdf
For more info visit: http://www.opensparc.net
Sunday, August 13, 2006
OpenAccess

OpenAccess adoption is gaining momentum within the industry. Many companies are deploying the technology within their design flows, or are rolling out their OpenAccess-supported applications.
OpenAccess is a community-driven initiative that provides an interoperability platform for complex IC design based on a common, open, and extensible architecture. This is achieved through
- Open standard application programming interface (API)
- Reference database implementation supporting that API
The initiative is driven by the OpenAccess Coalition, an organization comprised of world leaders in IC design. The OpenAccess Coalition operates under the governance and bylaws of Si2. Please visit www.si2.org/openaccess and www.openeda.si2.org for more information about OpenAccess.
Sunday, July 23, 2006
43rd DAC!
The 43rd Design Automation Conference (DAC) is the electronic design automation (EDA) industry's premier event that being hold these days in San Francisco. DAC features over 50 technical sessions covering the latest in design methodologies and EDA tool developments and an Exhibition and Demo Suite area with over 250 of the leading EDA, silicon and IP Providers.
DAC 43 Homepage: http://www.dac.com/43rd/index.html
DeepChip's famous "Must See List for DAC 2006": http://www.deepchip.com/gadfly/gad072006.html
Tuesday, July 18, 2006
SystemC IEEE Standard is Free
By making the IEEE 1666 LRM freely available worldwide, OSCI furthers its commitment to the rapid growth of a global community of system, semiconductor, intellectual property, embedded software and EDA companies.
The IEEE approved the IEEE 1666™ -2005 standard for SystemC on December 12, 2005.
Source: http://www10.edacafe.com/nbc/articles/view_article.php?section=CorpNews&articleid=289730
Tuesday, May 30, 2006
I'm busy...
Monday, May 08, 2006
OneSpin Solutions
- Verification Planning
- Design Conditioning
- Single Property Development
- Complete Property Set Development
Visit company website for more info: OpenSpin Solutions
Thursday, April 06, 2006
The Best VLSI Book
Thursday, March 30, 2006
Finally Ponte released the Yield Analyzer.
From offical press release "Ponte Solutions, Inc., the design-for-yield company, announced the availability of Yield Analyzer™ v2.0, a system with a unique model-based analysis technology that provides automated yield analysis and enables optimization of a design prior to its tape-out. Yield Analyzer reduces manufacturing cost and time-to-volume production of complex semiconductor ICs by revealing yield-sensitive areas of the design and enabling yield improvement at the design stage, prior to committing to expensive fabrication. "
Full press release: http://www.pontesolutions.com/?p=press&id=14
Tuesday, March 21, 2006
OpenSPARC T1 Released
By making the source for this design available engineering community to review and learn from, Sun expects that ideas around the multi-thread concepts can be explored more freely and openly, and that truly beneficial innovations can be achieved.
OpenSPARC T1 source components are covered under multiple open source licenses and can be downloaded from this page:
http://opensparc-t1.sunsource.net/download_hw.html
Monday, March 20, 2006
Synopsys completely supports SystemVerilog
Synopsys laid claim to being the first EDA vendor to provide a complete SystemVerilog flow. Company says that more than 150 companies are already using their SystemVerilog solutions in design and verification.
Synopsys products supporting the SystemVerilog standard now span the Galaxy Design and Discovery verification platforms, including Design Compiler for logic synthesis, the VCS comprehensive verification solution with Native Testbench, the Pioneer-NTB SystemVerilog testbench automation tool, the Formality equivalence checker, the Magellan hybrid formal analysis tool, and the Leda programmable RTL checker, Synopsys said. SystemVerilog support is also provided in the assertion-checker and base-class testbench building-block libraries that ship with Discovery products as well as in the VCS Verification Library.
VCS verification library, containing DesignWare verification IP, is the first to support testbenches created using SystemVerilog and the coverage-driven methodology defined in the Verification Methodology Manual (VMM) for SystemVerilog, the manual co-written by Synopsys and ARM Holdings plc.
Already started to read the VMM for SystemVerilog.
Full article: http://eet.com/news/design/showArticle.jhtml?articleID=183700833
Thursday, March 16, 2006
Photomask prices
For example, electron-beam reticle writing machines hover around the $10-$20 million range. Photomask inspection is the most expensive part of mask production. A full-blown mask inspection system can costs of around $30 million - each.
And in total, the capital cost for a single, leading-edge mask line is projected to be about $60 million for the 90-nm node alone. That is expected to jump from $68-$70 million for a single 65-nm mask line to about $80 million for a 45-nm reticle line.
Full article: http://eet.com/news/design/showArticle.jhtml?articleID=181503925
Wednesday, March 15, 2006
Incisive Plan-to-Closure Methodology
The webinar now is archived and can be accessed from Cadence website.
More on Plan-to-Closure Methodology can be found in this whitepaper:

Tuesday, March 14, 2006
Computer Aids for VLSI Design
Came upon a nice text on VLSI EDA tools. Written in 1994, the book can be good introduction to the subject.
Here is the contents:
- The Characteristics of Digital Electronic Design
- Design Environments
- Representation
- Synthesis Tools
- Static Analysis Tools
- Dynamic Analysis Tools
- The Output of Design Aids
- Programmability
- Graphics
- Human Engineering
- Electric
- Appendices
To book is available online here:
Computer Aids for VLSI Design
The last chaper about Electric tool by Static Free Software. The tool is free and can be downloaded from http://www.staticfreesoft.com/.
Cadence webinar
- Incisive Plan-to-Closure Methodology
- Overview SystemVerilog Design Team Methodology
I like Cadence. Will see how they run webinars.