Finally Ponte released the Yield Analyzer.

Good news! Today read in EEtimes headlines "Design-for-yield-focused startup Ponte Solutions Inc. Wednesday (March 29) released version 2.0 of its Yield Analyzer model-based yield analysis tool. ". Wow!

From offical press release "Ponte Solutions, Inc., the design-for-yield company, announced the availability of Yield Analyzer™ v2.0, a system with a unique model-based analysis technology that provides automated yield analysis and enables optimization of a design prior to its tape-out. Yield Analyzer reduces manufacturing cost and time-to-volume production of complex semiconductor ICs by revealing yield-sensitive areas of the design and enabling yield improvement at the design stage, prior to committing to expensive fabrication. "

Full press release: http://www.pontesolutions.com/?p=press&id=14

OpenSPARC T1 Released

Sun released the open source version of the UltraSPARC T1 design called "OpenSPARC T1". The UltraSPARC T1 processor with CoolThreads technology is the highest-throughput and most eco-responsible processor ever created.

By making the source for this design available engineering community to review and learn from, Sun expects that ideas around the multi-thread concepts can be explored more freely and openly, and that truly beneficial innovations can be achieved.

OpenSPARC T1 source components are covered under multiple open source licenses and can be downloaded from this page:
http://opensparc-t1.sunsource.net/download_hw.html

Synopsys completely supports SystemVerilog

Synopsys laid claim to being the first EDA vendor to provide a complete SystemVerilog flow. Company says that more than 150 companies are already using their SystemVerilog solutions in design and verification.

Synopsys products supporting the SystemVerilog standard now span the Galaxy Design and Discovery verification platforms, including Design Compiler for logic synthesis, the VCS comprehensive verification solution with Native Testbench, the Pioneer-NTB SystemVerilog testbench automation tool, the Formality equivalence checker, the Magellan hybrid formal analysis tool, and the Leda programmable RTL checker, Synopsys said. SystemVerilog support is also provided in the assertion-checker and base-class testbench building-block libraries that ship with Discovery products as well as in the VCS Verification Library.

VCS verification library, containing DesignWare verification IP, is the first to support testbenches created using SystemVerilog and the coverage-driven methodology defined in the Verification Methodology Manual (VMM) for SystemVerilog, the manual co-written by Synopsys and ARM Holdings plc.

Already started to read the VMM for SystemVerilog.

Full article: http://eet.com/news/design/showArticle.jhtml?articleID=183700833

Photomask prices

Do you know how much photomask production tools cost?

For example, electron-beam reticle writing machines hover around the $10-$20 million range. Photomask inspection is the most expensive part of mask production. A full-blown mask inspection system can costs of around $30 million - each.

And in total, the capital cost for a single, leading-edge mask line is projected to be about $60 million for the 90-nm node alone. That is expected to jump from $68-$70 million for a single 65-nm mask line to about $80 million for a 45-nm reticle line.

Full article: http://eet.com/news/design/showArticle.jhtml?articleID=181503925

Incisive Plan-to-Closure Methodology

Tonight attended Cadence webinar "Incisive Plan-to-Closure Methodology Overview" from Incisive Plan-to-Closure Methodology Technical Webinar Series. When called in, a woman voice asked password and my name. Then I joined to the presentation. Overall the webinar was quite good. The Microsoft Live Meeting was used and Skype for toll free phone call.
The webinar now is archived and can be accessed from Cadence website.
More on Plan-to-Closure Methodology can be found in this whitepaper:
Incisive plan-to-closure methodology: Design Team Verification

Computer Aids for VLSI Design

Came upon a nice text on VLSI EDA tools. Written in 1994, the book can be good introduction to the subject.

Here is the contents:

1. The Characteristics of Digital Electronic Design
2. Design Environments
3. Representation
4. Synthesis Tools
5. Static Analysis Tools
6. Dynamic Analysis Tools
7. The Output of Design Aids
8. Programmability
9. Graphics
10. Human Engineering
11. Electric
12. Appendices

To book is available online here:
Computer Aids for VLSI Design

The last chaper about Electric tool by Static Free Software. The tool is free and can be downloaded from http://www.staticfreesoft.com/.

Cadence webinar

Today, for the first time, have registraed to Cadence webinar - IPCM Verification Planning & Management. IPCM stands for Incisive Plan-to-Closure Methodology. Also it's possible to attend past webinars from Cadence site:

• Incisive Plan-to-Closure Methodology
• Overview SystemVerilog Design Team Methodology

I like Cadence. Will see how they run webinars.

Opened!

Being inspired by electronics technology, I'm opening this blog to setup engineering community in Armenia. Welcome!