Synopsys completely supports SystemVerilog

Synopsys laid claim to being the first EDA vendor to provide a complete SystemVerilog flow. Company says that more than 150 companies are already using their SystemVerilog solutions in design and verification.

Synopsys products supporting the SystemVerilog standard now span the Galaxy Design and Discovery verification platforms, including Design Compiler for logic synthesis, the VCS comprehensive verification solution with Native Testbench, the Pioneer-NTB SystemVerilog testbench automation tool, the Formality equivalence checker, the Magellan hybrid formal analysis tool, and the Leda programmable RTL checker, Synopsys said. SystemVerilog support is also provided in the assertion-checker and base-class testbench building-block libraries that ship with Discovery products as well as in the VCS Verification Library.

VCS verification library, containing DesignWare verification IP, is the first to support testbenches created using SystemVerilog and the coverage-driven methodology defined in the Verification Methodology Manual (VMM) for SystemVerilog, the manual co-written by Synopsys and ARM Holdings plc.

Already started to read the VMM for SystemVerilog.

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